1. Field of the Invention
The present invention relates to molding technique for copper interconnecting wires by electrochemical displacement deposition on the pre-shaped metal layer, and more particularly to a molding technique for copper interconnecting wires by electrochemical displacement deposition on the pre-shaped metal layer for ultra large scale integrated circuit (ULSI).
2. Description of Related Art
The conventional methods of copper growth for very large scale integrated circuit (VSLI) and ULSI respectively comprise physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless deposition, etc., wherein the copper formed by other methods. However, the step coverage of the copper grown in the grooves in the surface of wafer by PVD is not even, and the copper grown by CVD has a good coverage, but not pure such that the copper growth by CVD has a resistance higher than that of the copper grown by PVD. Furthermore, the prescription of dry etching cannot create a reactant with high volatility such that the copper film cannot be etched and formed leading wires on the surface of the wafer.
Consequently, major manufacturers use damascene process to grow copper. With reference to FIG. 4, an underlying dielectric layer (72) is formed on a substrate (71). Multiple grooves (73) are defined in the underlying dielectric layer (72) by photolithography etching and correspond to the copper interconnecting wires. A copper layer (74) is electroplated on the underlying dielectric layer (72) so that the copper interconnecting wires (741) is formed in the multiple grooves (73) after chemical mechanical polishing (CMP) for grinding the unnecessary portion of the copper layer (74).
However, the manufacturer must grind the copper layer (74) one after one by CMP in the current technique. Consequently, the conventional method for forming the copper interconnecting wires by CMP takes a lot of manufacturing cost and has an output in a low rate, and needs to be advantageously altered.
With reference to FIG. 5, for solving the above problems of damascene process, an electrochemical displacement deposition (EDD) is used. As shown in FIG. 5, an underlying dielectric layer (82) is piled upon a substrate (81) and multiple grooves (821) are defined in the top of the underlying dielectric layer (82) by etching. A mask (83) is coated on the surface of the underlying dielectric layer (82) and a poly-silicone layer (84) is piled on the mask (83). The poly-silicone layer (84) is ground to be flushed with the mask (83) so that each groove (821) is fill with poly-silicone. Finally, the solution containing hydrofluoric acid (BOE) and cupric sulphate (CuSO4) is used to execute the electrochemical displacement deposition to the remained poly-silicone layer (84) to reduce the copper ions in the solution and collect on the surface of the mask (83). The reduced copper ions are used as the copper interconnecting wires. The chemical formula of the above chemical reaction is followed:Si+6F+2Cu2+→SiF62−+2Cu(s), Eredox=+1.45 eV
However, the copper grown by the method of the EDD has a high resistance and is difficult to be adhered on the surface of the wafer.
The present invention has arisen to mitigate and/or obviate the disadvantages of the conventional methods for growing copper interconnecting wire.